Temperature and voltage measurement for field test using an Aging-Tolerant monitor

Measuring temperature and voltage (T&V) in a current VLSI is very important in guaranteeing its reliability, because a large variation of temperature or voltage in field will reduce a delay margin and makes the chip behavior unreliable. This paper proposes a novel method of T&V measurement, which can be used for variety of applications, such as field test, online test, or hot-spot monitoring. The method counts frequencies of more than one ring oscillator (RO), which composes an aging-tolerant monitor. Then, the T&V are derived from the frequencies using a multiple regression analysis. To improve the accuracy of measurement, three techniques of an optimal selection of RO types, their calibration, and hierarchical calculation are newly introduced. In order to make sure the proposed method, circuit simulation in 180-, 90-, and 45-nm CMOS technologies is performed. In the 180-nm CMOS technology, the temperature accuracy is within 0.99 °C, and the voltage accuracy is within 4.17 mV. Furthermore, some experimental results using fabricated test chips with 180-nm CMOS technology confirm its feasibility

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test

Field test is performed in diverse environments, in which temperature varies across a wide range. As temperature affects a circuit delay greatly, accurate temperature monitors are required. They should be placed at various locations on a chip including hot spots. This paper proposes a flexible ring-oscillator-based monitor that accurately measures voltage as well as temperature at the same time. The measurement accuracy was confirmed by circuit simulation for 180 nm, 90 nm and 45 nm technologies. An experiment using test chips with 180 nm technology shows its feasibility.2014 IEEE 23rd Asian Test Symposium (ATS), 16-19 Nov. 2014, Hangzhou, Chin

Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA

Ring Oscillators are used for variety of purposes to enhance reliability on LSIs or FPGAs. This paper introduces an aging-tolerant design structure of ring oscillators that are used in FPGAs. The structure is able to reduce NBTI-induced degradation in a ring oscillator\u27s frequency by setting PMOS transistors of look-up tables in an off-state when the oscillator is not working. The evaluation of a variety of ring oscillators using Altera Cyclone IV device (60nm technology) shows that the proposed structure is capable of controlling degradation level as well as reducing more than 37% performance degradation compared to the conventional oscillators.The 20th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2014), Nov 19-21, 2014, Singapor

Multi-Cycle Test with Partial Observation on Scan-Based BIST Structure

Field test for reliability is usually performed with small amount of memory resource, and it requires a new technique which might be somewhat different from the conventional manufacturing tests. This paper proposes a novel technique that improves fault coverage or reduces the number of test vectors that is needed for achieving the given fault coverage on scan-based BIST structure. We evaluate a multi-cycle test method that observes the values of partial flip-flops on a chip during capture-mode. The experimental result shows that the partial observation achieves fault coverage improvement with small hardware overhead than the full observation.2011 Asian Test Symposium (ATS), 20-23 Nov. 2011, New Delhi, Indi

A Scan-Out Power Reduction Method for Multi-Cycle BIST

High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach that directly reduces scan-out power by modifying some flip-flops\u27 values in scan chains at the last capture. Experimental results show that the proposed method reduces scan-out power up to 30% with little loss of test coverage.2012 IEEE 21st Asian Test Symposium, 19-22 Nov. 2012, Niigata, Japa

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST

Multi-cycle test with partial observation for scan-based logic BIST is known as one of effective methods to improve fault coverage without increase of test time. In the method, the selection of flip-flops for partial observation is critical to achieve high fault coverage with small area overhead. This paper proposes a selection method under the limitation to a number of flip-flops. The method consists of structural analysis of CUT and logic simulation of test vectors, therefore, it provides an easy implementation and a good scalability. Experimental results on benchmark circuits show that the method obtains higher fault coverage with less area overhead than the original method. Also the relation between the number of selected flip-flops and fault coverage is investigated.27th IEEE ASIAN TEST SYMPOSIUM (ATS\u2718), 15-18 October 2018, Hefei, Chin

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.2016 IEEE 25th Asian Test Symposium (ATS), 21-24 Nov. 2016, Hiroshima, Japa

Path Delay Measurement with Correction for Temperature And Voltage Variations

Path delay measurement in field is useful for not only detection of delay-related faults but also prediction of aging-induced delay faults. In order to utilize the delay measurement results for fault detection and fault prediction, the measured delay must be corrected because the circuit delay is varied in field due to environment such as temperature or voltage variations. This paper proposes a method of BIST-based path delay measurement in which the influence of environmental variations is eliminated. An on-chip sensor measures temperature and voltage during delay measurement. Using information from the temperature and voltage sensor and pre-computed temperature and voltage sensitivities of the circuit delay, the measured delay value is corrected to a delay value that would be obtained under a fixed temperature and voltage. Evaluation for a test chip with 65nm CMOS technology implementing the proposed method shows that errors of measured delays brought by environmental variations could be reduced from 2419 to 211 ps in the range of 30 to 80 °C and 1.05 to 1.35 V. This paper also discusses application and feasibility for degradation detection of the proposed method.International Test Conference in Asia (ITC-Asia 2020), September 23-25, 2020, Taipei City, Taiwan（現地およびオンラインで開催

A selection method of ring oscillators for an on-chip digital temperature and voltage sensor

An on-chip digital sensor using three types of ring oscillators (ROs: Ring Oscillators) has been proposed to measure temperature and voltage of a VLSI. Each RO has inherent frequency characteristics with respect to temperature and voltage, which differ from those of the other two ROs. Measurement accuracy of the sensor depends on the combination of the ROs. This paper proposes a RO-selection method for the sensor with high accuracy. The proposed method takes particular note of temperature or voltage sensitivity as well as linearity of the RO characteristics. Evaluation experiments with SPICE simulation in 65 nm CMOS technology show that the temperature and voltage accuracies of the sensor are 2.744°C and 3.825mV, respectively, and the selected combination was a nearly optimal from a menu of many different ROs.The 3rd International Test Conference in Asia (ITC-Asia 2019), September 3-5, 2019Tokyo Denki University, Tokyo, Japa

On-chip delay measurement for in-field test of FPGAs

Avoidance of delay-related failures due to aging phenomena is an important issue of current VLSI systems. Delay measurement in field is effective for detection of aging-induced delay increase. This paper proposes a delay measurement method using BIST (Built-In Self-Test) in an FPGA. The proposed method consists of variable test timing generation using an embedded PLL, BIST-based delay measurement, and correction of the measured delay with reflecting temperature variance in field. In on-chip delay measurement of the proposed method, the fastest operating speed is checked by repeating delay test with several test timings. Because circuit delay is influenced by temperature during measurement, the measured delay is then corrected according to the temperature during testing. Based on test log including the corrected delay, delay degradation and aging detection can be grasped. In evaluation experiments of the propose method implemented on an Intel Cyclone IV FPGA device (60nm technology), variable test timing generation realized 96 ps timing step resolution (that is below 1% of the system clock), correction process for measured delay could reduce influence of temperature variation. Furthermore, its feasibility of the proposed method for aging detection is discussed in this paper.24th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2019), December 1-3, 2019, Kyoto, Japa